There are many steps required in manufacturing multi-level interconnects for integrated circuits (IC). Such steps include depositing conducting and insulating materials on a semiconductor wafer or workpiece followed by full or partial removal of these materials using photo-resist patterning, etching, and the like. After photolithography, patterning and etching steps, the resulting surface is generally non-planar as it contains many cavities or features such as vias, contact holes, lines, trenches, channels, bond-pads, and the like that come in a wide variety of dimensions and shapes. These features are typically filled with a highly conductive material before additional processing steps such as etching and/or chemical mechanical polishing (CMP) is/are performed. Accordingly, a low resistance interconnection structure is formed between the various sections of the IC after completing these deposition and removal steps multiple times.
Copper (Cu) and Cu alloys are quickly becoming the preferred materials for interconnections in ICs because of their low electrical resistivity and high resistance to electro-migration. Electrodeposition is one of the most popular methods for depositing Cu into the features on the workpiece surface. Therefore the present invention will be described for electroplating Cu although it is in general applicable for electroplating any other material. During a Cu electrodeposition process, specially formulated plating solutions or electrolytes are used. These solutions or electrolytes contain ionic species of Cu and additives to control the texture, morphology, and the plating behavior of the deposited material. Additives are needed to obtain smooth and well-behaved layers. There are many types of Cu plating solution formulations, some of which are commercially available. One such formulation includes Cu-sulfate (CuSO4) as the copper source (see for example James Kelly et al., Journal of The Electrochemical Society, Vol. 146, pages 2540-2545, (1999)) and includes water, sulfuric acid (H2SO4), and a small amount of chloride ions. As is well known, other chemicals, called additives, are generally added to the Cu plating solution to achieve desired properties of the deposited material. These additives get attached to or chemically or physically adsorbed on the surface of the substrate to be coated with Cu and therefore influence the plating there as we will describe below.
The additives in the Cu plating solution can be classified under several categories such as accelerators, suppressors/inhibitors, levelers, brighteners, grain refiners, wetting agents, stress-reducing agents, etc. In many instances, different classifications are often used to describe similar functions of these additives. Today, solutions used in electronic applications, particularly in manufacturing ICs, contain simpler two-component additive packages (e.g., see Robert Mikkola and Linlin Chen, “Investigation of the Roles of the Additive Components for Second Generation Copper Electroplating Chemistries used for Advanced Interconnect Metallization”, Proceedings of the International Interconnect Technology Conference, pages 117-119, Jun. 5-7, 2000). These formulations are generically known as suppressors and accelerators. Some recently introduced packages for example Via-Form chemistry marketed by Enthone, and Nano-Plate chemistry marketed by Shipley, also include a third component called a leveler.
Suppressors or inhibitors are typically polymers and are believed to attach themselves to the workpiece surface at high current density regions, thereby forming, in effect, a high resistance film, increasing polarization there and suppressing the current density and therefore the amount of material deposited thereon. Accelerators, on the other hand, enhance Cu deposition on portions of the workpiece surface where they are adsorbed, in effect reducing or eliminating the inhibiting function of the suppressor. Levelers are added in the formulation to avoid formation of bumps or overfill over dense and narrow features as will be described in more detail hereinafter. Chloride ions themselves affect suppression and acceleration of deposition on various parts of the workpiece (See Robert Mikkola and Linlin Chen, “Investigation” Proceedings article referenced above). The interplay between all these additives in-part determines the nature of the Cu deposit.
The following figures are used to more fully describe a conventional electrodeposition method and apparatus. FIG. 1 illustrates a cross-sectional view of an example workpiece 3 having an insulator 2 formed thereon. Using conventional deposition and etching techniques, features such as a dense array of small vias 4a, 4b, 4c and a dual damascene structure 4d are formed on the insulator 2 and the workpiece 3. In this example, the vias 4a, 4b, 4c are narrow and deep; in other words, they have high aspect ratios (i.e., their depth to width ratio is large). Typically, the widths of the vias 4a, 4b, 4c may be sub-micron. The dual-damascene structure 4d, on the other hand, has a wide trench 4e and a small via 4f on the bottom. The wide trench 4e has a small aspect ratio.
FIGS. 2a-2c illustrate a conventional method for filling the features of FIG. 1 with Cu. FIG. 2a illustrates the exemplary workpiece of FIG. 1 having various layers disposed thereon. For example, this figure illustrates the workpiece 3 and the insulator 2 having deposited thereon a barrier/glue or adhesion layer 5 and a seed layer 6. The barrier/glue layer 5 may be tantalum, nitrides of tantalum, titanium, tungsten, or TiW, etc., or combinations of any other materials that are commonly used in this field. The barrier/glue layer 5 is generally deposited using any of the various sputtering methods, by chemical vapor deposition (CVD) etc. Thereafter, the seed layer 6 is deposited over the barrier/glue layer 5. The seed layer 6 material may be copper or copper substitutes and may be deposited on the barrier/glue layer 5 using various methods known in the field.
In FIG. 2b, after depositing the seed layer 6, a conductive material 7 (e.g., copper layer) is electrodeposited thereon from a suitable plating bath. During this step, an electrical contact is made to the Cu seed layer and/or the barrier layer so that a cathodic (negative) voltage can be applied thereto with respect to an anode (not shown). Thereafter, the Cu material 7 is electrodeposited over the workpiece surface using the specially formulated plating solutions, as discussed above. It should be noted that the seed layer is shown as an integral part of the deposited copper layer 7 in FIG. 2b. By adjusting the amounts of the additives, such as the chloride ions, suppressor/inhibitor, and the accelerator, it is possible to obtain bottom-up Cu film growth in the small features.
As shown in FIG. 2b, the Cu material 7 completely fills the vias 4a, 4b, 4c, 4f and is generally conformal in the large trench 4e. Copper does not completely fill the trench 4e because the additives that are used in the bath formulation are not operative in large features. For example, it is believed that the bottom up deposition into the vias and other features with large aspect ratios occurs because the suppressor/inhibitor molecules attach themselves to the top portion of each feature opening to suppress the material growth thereabouts. These molecules cannot effectively diffuse to the bottom surface of the high aspect ratio features such as the vias of FIG. 1 through the narrow openings. Preferential adsorption of the accelerator on the bottom surface of the vias, therefore, results in faster growth in that region, resulting in bottom-up growth and the Cu deposit profile as shown in FIG. 2b. Without the appropriate additives, Cu can grow on the vertical walls as well as the bottom surface of the high aspect ratio features at the same rate, thereby causing defects such as seams and voids, as is well known in the industry.
Adsorption characteristics of the suppressor and accelerator additives on the inside surfaces of the low aspect-ratio trench 4e is not expected to be any different than the adsorption characteristics on the top surface or the field region 8 of the workpiece. Therefore, the Cu thickness at the bottom surface of the trench 4e is about the same as the Cu thickness over the field regions 8. Field region is defined as the top surface of the insulator in between the features etched into it.
As can be expected, to completely fill the trench 4e with the Cu material 7, further plating is required. FIG. 2c illustrates the resulting structure after additional Cu plating. In this case, the Cu thickness t3 over the field region 8 is relatively large and there is a step s1 from the field regions 8 to the top of the Cu material 7 in the trench 4e. Furthermore, if there is no leveler included in the electrolyte formulation, the region over the high aspect-ratio vias can have a thickness t4 that is larger than the thickness t3 near the large feature. This phenomena is called “overfill” and is believed to be due to enhanced deposition over the high aspect ratio features resulting from the high accelerator concentration in these regions. Apparently, accelerator species that are preferentially adsorbed in the small vias as explained before, stay partially adsorbed even after the features are filled. For IC applications, the Cu material 7 needs to be subjected to CMP or other material removal process so that the Cu material 7 as well as the barrier layer 5 in the field regions 8 are removed, thereby leaving the Cu material 7 only within the features as shown in 2d. The situation shown in FIG. 2d is an ideal result. In reality these material removal processes are known to be quite costly and problematic. A non-planar surface with thick Cu such as the one depicted in FIG. 2c has many drawbacks. First of all, removal of a thick Cu layer is time consuming and costly. Secondly, the non-uniform surface cannot be removed uniformly and results in dishing defects in large features as well known in the industry and as shown in FIG. 2e. 
Thus far, much attention has been focused on the development of Cu plating chemistries and plating techniques that yield bottom-up filling of small features on a workpiece. This is necessary because, as mentioned above, lack of bottom-up filling can cause defects in the small features. Recently, levelers have been added into the electrolyte formulations to avoid overfilling over high aspect ratio features. As bumps or overfill start to form over such features, leveler molecules are believed to attach themselves over these high current density regions i.e. bumps or overfill, and reduce plating there, effectively leveling the film surface. Therefore, special bath formulations and pulse plating processes have been developed to obtain bottom-up filling of the small features and reduction or elimination of the overfilling phenomenon.
A new class of plating techniques called Electrochemical Mechanical Deposition (ECMD) have been developed to deposit planar films over workpieces with cavities of all shapes, sizes and forms. Methods and apparatus to achieve thin and planar Cu deposits on electronic workpieces such as semiconductor wafers are invaluable in terms of process efficiency. Such a planar Cu deposit is depicted in FIG. 3. The Cu thickness t5 over the field regions 8 in this example is smaller than the traditional case as shown in FIG. 2c. Removal of the thinner Cu layer in FIG. 3 by CMP, etching, electropolishing or other methods would be easier, providing important cost savings. Dishing defects are also expected to be minimal in removing planar layers such as the one shown in FIG. 3.
In the recently issued U.S. Pat. No. 6,176,992, entitled “Method and Apparatus for Electrochemical Mechanical Deposition”, commonly owned by the assignee of the present invention, discloses in one aspect a technique that achieves deposition of the conductive material into the cavities on the workpiece surface while minimizing deposition on the field regions. This ECMD process results in planar material deposition.
U.S. patent application Ser. No. 09/740,701 filed on Dec. 18, 2000 entitled “Plating Method And Apparatus That Creates A Differential Between Additive Disposed On A Top Surface And A Cavity Surface Of A Workpiece Using An External Influence now U.S. Pat. No. 6,534,116” and is also assigned to the same assignee as the present invention, describes in one aspect an ECMD method and apparatus that causes a differential in additives to exist for a period of time between a top surface and a cavity surface of a workpiece. While the differential is maintained, power is applied between an anode and the workpiece to cause greater relative plating of the cavity surface than the top surface.
Other applications filed that relate to specific improvements in various aspects of ECMD processes include U.S. patent application Ser. No. 09/511,278 entitled “Pad Designs and Structures for a Versatile Materials Processing Apparatus” filed Feb. 23, 2000 now U.S. Pat. No. 6,413,388, U.S. patent application Ser. No. 09/621,969 entitled “Pad Designs and Structures With Improved Fluid Distribution” filed Jul. 21, 2000 now U.S. Pat. No. 6,413,403; “Mask Plate Design” filed on the same day as this application, and which also is based on priority provisional application No. 60/272,791 filed Mar. 1, 2001. U.S. patent application Ser. No. 09/671,800 entitled “Method to Minimize and/or Eliminate Conductive Material Coating Over the Top Surface of a Patterned substrate and Layer Structure Made Thereby filed Sept. 28, 2000 now pending and U.S. patent application Ser. No. 09/760,757 entitled “Method and Apparatus for Controlling Thickness Uniformity of Electroplated Layer filed Jan. 17, 2001 now U.S. Pat. No. 6,610,190, all of which applications are assigned to the same assignee as the present invention.
While the above-described ECMD processes provide numerous advantages, further refinements that allow for greater control of material deposition in areas corresponding to various cavities, to yield new and novel conductor structures, are desirable.